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In this role, you will be at the center of a PHY design effort interfacing with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class PHY designs. You will be required to do physical designs of best in class PHY design.
As a Physical Design, engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Create full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.
- Deep Understanding of all aspects of Physical construction, Integration and Physical Verification
- Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
- The ideal candidate should have at least 5+ years of Design experience on high PHY and/or SOC designs
- Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
- Proven Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools
- Experience in developing and implementing Power-grid and Clock specifications
- Deep Understanding of scripting languages such as Perl/Tcl
- Relevant working knowledge of Extraction and STA methodology and tools
Vacancy Type: Full Time
Job Location: Bryan, TX, US
Application Deadline: N/A